1. Field
Embodiments included herein generally relate to debugging a chip (also referred to herein as “chip debug”). More particularly, embodiments relate to chip debug during power gating events.
2. Background
As the footprint and complexity of semiconductor chips grow, Design for Debug (DFD) has increasingly grown in importance to ensure the chip's speedy time to market. One DFD technique instantiates one or more debug wrappers within functional blocks of the chip. Debug wrappers are hardware- and/or software-based modules placed in one or more locations of the chip for debug purposes. These debug wrappers require signal observation and a daisy chain connection to an internal or external logic analyzer/trace capture buffer. Oftentimes, this DFD technique is implemented in chip designs with power gating techniques (e.g., system-on-a-chip integrated circuits) used to save power during different modes of operation (e.g., standby mode of operation). Such power gating techniques can impact and complicate debug observation. For example, the functional blocks are removed from the chip's power supply rails using sleep transistors. Due to the daisy chain configuration of the DFD technique, the debug/observation signals of functional blocks that are not powered down, but upstream of functional blocks that are powered down, cannot be observed.